The present invention generally relates to a peak hold and calibration circuit, and more particularly, to a peak hold and calibration circuit for use in measuring the signals in a digital multi-meter implemented by using very large scale integration (VLSI) technology.
In a general electronic circuit system, a peak hold circuit that uses a peak maximum circuit and a peak minimum circuit is used to measure the maximum voltage value and the minimum voltage value of an analog input signal.
Please refer to FIG. 1, which illustrates the definitions of a maximum voltage value and a minimum voltage value of an analog input signal. The currently used peak hold circuit that is applied to measure the maximum voltage value and the minimum voltage value of an analog input signal in a digital multi-meter is implemented by using discrete components.
Please refer to FIG. 2A and FIG. 2B, which are two detailed circuits that illustrate the peak maximum circuit and the peak minimum circuit of the conventional peak hold circuit of the prior art. To be more specific, FIG. 2A is a peak maximum circuit 10, and FIG. 2B is a peak minimum circuit 20.
As can be seen in FIG. 2A, the peak maximum circuit 10 comprises an operational amplifier 12, a diode 14, and a capacitor 16. The input signal VIN is applied directly to the non-inverting input terminal of the operational amplifier 12 while the output terminal of the operational amplifier 12 is connected to the positive terminal of the diode 14 that is further connected to the inverting input terminal of the operational amplifier 12 and the capacitor 16.
When the input voltage VIN is higher than the output voltage VOUT, the logic state of the output of the operational amplifier 12 is xe2x80x9chighxe2x80x9d. In the meantime, the diode 14 is turned on and the output voltage VOUT follows the input voltage VIN. In this case, the output voltage VOUT equals to the input voltage VIN.
On the contrary, when the input voltage VIN is lower than the output voltage VOUT, the logic state of the output of the operational amplifier 12 is xe2x80x9clowxe2x80x9d. In the meantime, the diode 14 is off and the capacitor 16 maintains the voltage of the output voltage VOUT. Once the input voltage VIN increases to be higher than the output voltage VOUT, the output voltage VOUT follows the input voltage VIN again.
Moreover, as shown in FIG. 2B, the peak minimum circuit 20 comprises an operational amplifier 22, a diode 24, and a capacitor 26. The input signal VIN is applied directly to the non-inverting input terminal of the operational amplifier 22 while the output terminal of the operational amplifier 22 is connected to the negative terminal of the diode 24 that is further connected to the inverting input terminal of the operational amplifier 22 and the capacitor 26.
When the input voltage VIN is lower than the output voltage VOUT, the logic state of the output of the operational amplifier 22 is xe2x80x9clowxe2x80x9d. In the meantime, the diode 24 is turned on and the output voltage VOUT follows the input voltage VIN. In this case, the output voltage VOUT equals to the input voltage VIN.
On the contrary, when the input voltage VIN is higher than the output voltage VOUT, the logic state of the output of the operational amplifier 22 is xe2x80x9chighxe2x80x9d. In the meantime, the diode 24 is off and the capacitor 26 maintains the voltage of the output voltage VOUT. Once the input voltage VIN decreases to be lower than the output voltage VOUT, the output voltage VOUT follows the input voltage VIN again.
However, the conventional peak hold circuit demands critical characteristics of the diode, therefore the diode needs to have short switching time, small parasitic capacitance, and small leakage current. Such a diode is hardly found. In addition, the capacitor that matches such a diode well is generally a holding capacitor that has a greater capacitance. Therefore, the peak hold signal is slow speed and the system is high power-consuming.
Accordingly, the conventional peak hold circuit implemented by using discrete components and composed of an operational amplifier, a diode, and a capacitor has several problems in that the peak hold circuit has higher fabricating cost, less economic profit and higher power consumption. Also the diode which has short switching time, small parasitic capacitance, and small leakage current is hardly found.
In order to overcome the problems that have been previously discussed above, the present invention has been proposed and relates to a peak hold and calibration circuit for use in measuring the signals in a digital multi-meter so as to solve the problems that occur in the conventional digital multi-meter of the prior art.
Accordingly, it is the main object of the present invention to provide a peak hold circuit for use in measuring the signals in a digital multi-meter so as to solve the problem in that the peak hold circuit implemented by using discrete components has higher fabricating cost, less economic profits and higher power consumption. Also diode which has short switching time, small parasitic capacitance, and small leakage current is hardly found.
In order to accomplish the foregoing objects, the present invention provides a peak hold circuit for use in measuring the signals in a digital multi-meter, which can be implemented by using an integrated circuit (to be abbreviated as xe2x80x9cICxe2x80x9d here below) and a capacitor, wherein said IC is connected to said capacitor; wherein said IC comprises an operational amplifier, and a switching circuit; wherein a first voltage is applied to one input terminal of said operational amplifier and the other input terminal of said operational amplifier is connected to the feedback network while the output terminal of said operational amplifier is connected to said switching circuit; wherein the output of said switching circuit is a second voltage and connected to said capacitor. The peak hold and calibration circuit for use in measuring the signals in a digital multi-meter of the present utilizes only a few components; thus it has lower fabricating cost, higher economic profit and lower power consumption. Also this invention doesn""t need to the diode which has short switching time, small parasitic capacitance, and small leakage current.
It is preferable that said switching circuit comprises a transistor, which can provide a current that is large enough to charge said capacitor.
It is preferable that said peak hold circuit for use in measuring the signals in a digital multi-meter comprises a resistor, which is connected to said transistor so as to prevent said second voltage from overshooting.
It is preferable that said transistor is an n-channel field effect transistor (to be abbreviated as xe2x80x9cFETxe2x80x9d here below); said first voltage is applied to the non-inverting input terminal of said operational amplifier; the inverting input terminal of said operational amplifier is connected to the feedback network; the output terminal of said operational amplifier is connected to the gate of said n-channel FET.
It is preferable that the drain of said n-channel FET is connected to the highest voltage terminal of the circuit and the source is connected to said resistor; the other terminal of said resistor is connected to said capacitor; and a low noise direct current (DC) voltage of the circuit is applied to the other terminal of said capacitor.
It is preferable that before the measurement, said second voltage is set to be lower than the lowest voltage in the effective measuring range.
It is preferable that when said first voltage is higher than said second voltage, the logic state of the output of said operational amplifier is xe2x80x9chighxe2x80x9d. In the meantime, said n-channel FET is turned on and said second voltage follows said first voltage.
It is preferable that when said first voltage is lower than said second voltage, the logic state of the output of said operational amplifier is xe2x80x9clowxe2x80x9d. In the meantime, said n-channel FET is off and said capacitor maintains the voltage of said second voltage.
It is preferable that once said first voltage increases to be higher than said second voltage, said second voltage follows said first voltage again.
It is preferable that said transistor is a p-channel FET; said first voltage is applied to the non-inverting input terminal of said operational amplifier; the inverting input terminal of said operational amplifier is connected to the feedback network; the output terminal of said operational amplifier is connected to the gate of said p-channel FET.
It is preferable that the drain of said p-channel FET is connected to the lowest voltage terminal of the circuit and the source is connected to said resistor; the other terminal of said resistor is connected to said capacitor; and a low noise direct current (DC) voltage of the circuit is applied to the other terminal of said capacitor.
It is preferable that before the measurement, said second voltage is set to be higher than the highest voltage in the effective measuring range.
It is preferable that when said first voltage is lower than said second voltage, the logic state of the output of said operational amplifier is xe2x80x9clowxe2x80x9d. In the meantime, said p-channel FET is turned on and said second voltage follows said first voltage.
It is preferable that when said first voltage is higher than said second voltage, the logic state of the output of said operational amplifier is xe2x80x9chighxe2x80x9d. In the meantime, said p-channel FET is off and said capacitor maintains the voltage of said second voltage.
It is preferable that once said first voltage decreases to be lower than said second voltage, said second voltage follows said first voltage again.
It is preferable that said transistor is a p-channel FET; said first voltage is applied to the inverting input terminal of said operational amplifier; the non-inverting input terminal of said operational amplifier is connected to the feedback network; the output terminal of said operational amplifier is connected to the gate of said p-channel FET.
It is preferable that the source of said p-channel FET is connected to the highest voltage terminal of the circuit and the drain is connected to said resistor; the other terminal of said resistor is connected to said capacitor; and a low noise direct current (DC) voltage of the circuit is applied to the other terminal of said capacitor.
It is preferable that before the measurement, said second voltage is set to be lower than the lowest voltage in the effective measuring range.
It is preferable that when said first voltage is higher than said second voltage, the logic state of the output of said operational amplifier is xe2x80x9clowxe2x80x9d. In the meantime, said p-channel FET is turned on and said second voltage immediately follows said first voltage.
It is preferable that when said first voltage is lower than said second voltage, the logic state of the output of said operational amplifier is xe2x80x9chighxe2x80x9d. In the meantime, said p-channel FET is off and said capacitor maintains the voltage of said second voltage.
It is preferable that once said first voltage increases to be higher than said second voltage, said second voltage follows said first voltage again.
It is preferable that said transistor is an n-channel FET; said first voltage is applied to the inverting input terminal of said operational amplifier; the non-inverting input terminal of said operational amplifier is connected to the feedback network; the output terminal of said operational amplifier is connected to the gate of said n-channel FET.
It is preferable that the source of said n-channel FET is connected to the lowest voltage terminal of the circuit and the drain is connected to said resistor; the other terminal of said resistor is connected to said capacitor; and a low noise direct current (DC) voltage of the circuit is applied to the other terminal of said capacitor.
It is preferable that before the measurement, said second voltage is set to be higher than the highest voltage in the effective measuring range.
It is preferable that the substrate of said n-channel FET is connected to the lowest voltage terminal of the circuit.
It is preferable that when said first voltage is lower than said second voltage, the logic state of the output of said operational amplifier is xe2x80x9chighxe2x80x9d. In the meantime, said n-channel FET is turned on and said second voltage immediately follows said first voltage.
It is preferable that when said first voltage is higher than said second voltage, the logic state of the output of said operational amplifier is xe2x80x9clowxe2x80x9d. In the meantime, said n-channel FET is off and said capacitor maintains the voltage of said second voltage.
It is preferable that once said first voltage decreases to be lower than said second voltage, said second voltage follows said first voltage again.
The present invention further provides a peak hold and calibration circuit for use in measuring the signals in a digital multi-meter, which can be implemented by using an integrated circuit (IC) and a capacitor, wherein said IC is connected to said capacitor; wherein said IC comprises an operational amplifier, a transistor, and a resistor; wherein a low noise direct current (DC) voltage of the circuit is applied to the inverting input terminal of said operational amplifier and the non-inverting input terminal of said operational amplifier is connected to the feedback network while the output terminal of said operational amplifier is connected to the gate of said transistor, which can provide a current that is large enough to charge said capacitor; wherein said resistor is connected to said transistor and said capacitor at the both terminals so as to prevent said second voltage from overshooting.
It is preferable that said transistor is a p-channel FET, the source of which is connected to the highest voltage terminal of the circuit; the drain of which is connected to one terminal of said resistor and the other terminal of said resistor is connected to said capacitor, to which a low noise direct current (DC) voltage of the circuit is applied.
It is preferable that a low noise direct current (DC) voltage (GND) of the circuit is applied to the inverting input terminal of said operational amplifier and the non-inverting input terminal of said operational amplifier is connected to the feedback network, therefore the output voltage is the input offset voltage of said operational amplifier.
It is preferable that said transistor is an n-channel FET, the source of which is connected to the lowest voltage terminal of the circuit; the drain of which is connected to one terminal of said resistor and the other terminal of said resistor is connected to said capacitor, to which a low noise direct current (DC) voltage of the circuit is applied.
It is preferable that the substrate of said n-channel FET is connected to the lowest voltage terminal of the circuit.
It is preferable that a low noise direct current (DC) voltage (GND) of the circuit is applied to the inverting input terminal of said operational amplifier and the non-inverting input terminal of said operational amplifier is connected to the feedback network, therefore the output voltage is the input offset voltage of said operational amplifier.